• Drive technical direction for PCIe validation, power/thermal diagnostics, and stress-testing frameworks that run across manufacturing, vetting, and production environments. • Own subsystems end-to-end: from design through implementation, testing, deployment, and operational excellence at fleet scale.

You will define the hardware that runs the world's largest AI training workloads. Your designs span electrical, thermal, mechanical, power, and signal integrity across GPU-accelerated platforms. You will drive validation from first silicon through fleet-scale deployment, triage failures correlating across PCIe, power delivery, memory, and accelerator interconnects, and feed root cause findings back into design improvements. When a new server platform launches at a large scale, the architecture,

include development and validation of TAP/JTAG and IJTAG infrastructures, Boundary Scan (BSCAN), MBIST, Scan/ATPG methodologies, and associated test collateral such as ICL, PDL, BSDL, and ATPG patterns. The role requires driving test access, pattern generation, coverage optimization, memory test validation, and debug of scan, at-speed, and silicon bring-up issues while ensuring robust DFT integration across the product lifecycle.